View AD392_1082672.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ANALOG W DEVICES
FEATURES Data Readback Capability Four Complete, Voltage Output, 12-Bit DACs in One 32-Pin Hermetic Package Fast Bus Access: 40ns max, Tmin-Tmax Asynchronous Reset to Zero Volts Minimum of Two TTL Load Drive (Readback Mode) Double-Buffered Data Latches Monotonicity Guaranteed TminoT max Linearity Error :t:1/2LSB Low Digital-to-Analog Feedthrough, 2nV sec typ Factory Trimmed Gain and Offset Low Cost
Complete uad Q 12-Bit Of Converter A withReadback
OBS
PRODUCT DESCRIPTION The AD392 is a quad I2-bit, high-speed, voltage output digital-toanalog converter with readback in a 32-pin hermetically sealed package. The design is based on a custom IC interface to complete I2-bit DAC chips which reduces chip count and provides high reliability. The AD392 is ideal for systems requiring digital control of many analog voltages and for the monitoring of these analog voltages especially where board space is a premium. Such applications include ATE, robotics, process controllers and precision fIlters.
OLE
PRODUCT HIGHLIGHTS 1. The AD392 is packaged in a 32-pin DIP and is a complete solution to space constraint multiple DAC applications. 2. Readback capability provides system monitor of DAC output useful in ATE, robotics or any closed-loop system. 3. Fast bus access time of 40ns maximum allows for fast system updating compatible with high-speed microprocessing.
Featuring maximum access time of 40ns, the AD392 is capable of interfacing to the fastest of microprocessors. The readback capability provides a diagnostic check between the data sent from the microprocessor and the actual data received and transferred to the DAC. When RESET is low, all four DACs are simultaneously set to (bipolar) zero providing a known starting point. The AD392 is laser-trimmed to :!:1/2LSB integral linearity and :!:ILSB max differential linearity at + 25C. Monotonicity is guaranteed over the full operating temperature range. The high initial accuracy and stability over temperature are made possible by the use of precision thin-fIlm resistors. The individual DAC registers are accessed by the address lines AO and Al and control lines CS and 2ND UP. These control signals permit the registers of the four DACs to be loaded sequentially and the outputs to be simultaneously updated. The AD392 outputs are calibrated for a :!:lOV output range with positive true offset binary input coding. The AD392 is packaged in a 32-lead ceramic package and is hermetically sealed. The AD392 is specified for operation over the 0 to + 70C temperature range.
4. Simultaneous reset to zero volts output is extremely useful for system calibration or simply when all DAC outputs must initially start at zero volts. 5. Readback drive capability of two TTL loads virtually eliminates the need to buffer. 6. Each DAC is independently addressable, providing a versatile control architecture for simple interface to microprocessors.
TE
7. Monolithic DAC chips provide excellent linearity and guaranteed monotonicity over the full operating temperature range. 8. Low digital-to-analog feedthrough (2nV sec typ) is maintained to assure DAC accuracy. 9. New pin stake package provides a low-cost solution to cost constraint applications.
Information furnished by Analog Devices is believed to be accurate and reliable. However. no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106 Tel: 617/329-4700 TWX:710/394-6577 West Coast Mid-West Texas 714/641-9391 3121350-9399 2141231-5094
SPECIFICATIONS = + Nee
Parameter DATA INPUTS (Pins 1-13, 16-18,30-32) TTL Compatible Input Voltage Bit ON (Logic "I") Bit OFF (Logic "0") Input Current + 25C
T nUnto T max
15V.
VEE
= -15V,
AD392
Voo
=
+ 5V.
TA
+ 25"C, unlessothelWise specified)
Min
Max
+2.0 DGND -2 -20
+Voo +0.8 +2 +20
V V J.LA J.LA
Voo = 5.25V Voo = 4.75V VIN = VooorGND VIN = VooorGND
OBS
T nUnto T max
Bidirectional Outputs (Pins 2-13) Voltage Output Low (IoL = +4.0mA) Voltage Output High (IoH = -4.0mA) Tristate Output Leakage
0 +2.4 -20 ::,::10
+0.4 Voo +20 +5 +40 ::'::0.05 ::'::0.025 ::,::0.025 ::'::0.25 ::'::0.5 +0.1 +0.05 +0.5 +1
V V J.LA V mA mA %ofFSR %ofFSR %ofFSR LSB LSB See Note I
DAC Output Voltage Range Current Range Short Circuit Current
-5
Gain Error Offset Bipolar Zero Integral Linearity Error Differential Linearity Error TEMPERATURE PERFORMANCE Gain Drift Offset Drift Integral Linearity Error
T nUnto T max
-0.1 -0.05
-0.5 -1 -25 -25
Differential Linearity Error
J
-1 +1 LSB -Monotonicity Guaranteed Over Full Temperature Range-
Settling Time (to ::':: /2LSB) 1 Change All Register Inputs From +5VtoOV/OVto +5V For LSB Change Slew Digital-to-Analog Glitch Impulse Crosstalk +Vcc, -VEE +Voo Current (All Digital Inputs DGND or + VooONL Y, No Load) Ice lEE 100 Power Dissipation POWER SUPPLY GAIN SENSITIVITY + Vcc, Voo, - VEE Operating (Full SpecificatIons) Storage NOTES 'VOUT VooorDGND. = 0 -65
OLE
::'::20 ::,::20 +25 +25 ppm FSRloC ppm FSRlOC I 10 2 0.1 4 2 J.Ls J.Ls V/J.LS nVsec LSB V V ::':: 6.5 1 +5.5 26 62 7.2 1356 44 82 13 1955 0.002 +70 + 150 mA mA mA mW %FS/%Vs C C
See Note 2
TE
See Note 3 See Note 4
::':: 3.5 1 +4.5
See Note 5 See Note 6
-
2 Referenced to trailing rising edge ofWR. 3Digital-to-Analog Glitch Impulse: This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. Specified as the area of the glitch in nV sees. 'Crosstalk is deemed as the change in anyone output as a result of any other output being driven from -IOVto + IOV intoa2kO load. 'Ojc approximately lOoCIW. 6+VCC, +Voo, -VEEare :tIO%. Specifications subject to change without notice.
-2-
I.!,,'
-
ABSOLUTEMAXIMUMRATINGS.
+ Va:: to AGND (Any DAC) - VEEto AGND (Any DAC)
. . . . . . . . . . . . 0 to
. . . . . . . . . . . . 0 to
+ 18V -18V
+VDDtoDGND
-0.3Vto+7V
Digital Inputs to DGND (Pins 1-13, 16-18, 30-32) Analog Outputs (Pins 20,22,26,28)
. . . . . . -O.3Vto +7V
IndefInite
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stess rating only and functional operation at or above this specification is not implied. Exposure to above maximum rating conditions for extended periods may affect device reliability.
Short Circuit Duration. (+ Va::, - VEEorAGND)
.........
Storage Temperature. . . . . . . . . . . . - 65C to + 150C
OBS
PACKAGE OUTLINE
I--I 1.592140.441 f58a i4O:3Jj
CAUTION: ESD (Electro-Static-Discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed.
Dimensions shown in inches and (mm).
.I
11000000000000000011
--looooooooooooooo I
PINI IDENTIFIER
--",..rJ o:75a [l
~~
lono. 1092 12774}
'II I
~ ...l-0.018
1:B86i47:9Oj U14(43.5'}
OLE J
0.155 --L (3.941
PIN CONFIGURATION
.
0.020~
-il-
~~.
(0.461
0.0'610.911
0.032 (0.811
--1I0.10512.67)
0.095 12.41)
-, ~.~~ ::~~~:
TI--~::~ g~:~:-1
'ii'
'(
TE
AD392
TOP VIEW (Not to Scalel
lID
Model AD392JV
ORDERING GUIDE Temperature Linearity Error Range Gain Error T min- max T Oto + 70C :t4LSB :tlLSB
Quantity 1-24 25-99 100+
Price
$151.00 $132.00 $ 99.00
-3-
Theoryof Operation
The AD392 is a quad 12-bit digital-to-analog converter with readback capability. The analog portion of the AD392 includes four bipolar process digital-to-analog converters. Each DAC contains current steering switches and a resistor ladder network which is laser-wafer trimmed for 12-bit accuracy. A precision output amplifier for voltage out operation and an internal highly stable voltage reference are all integrated on a single chip. The DAC is fIXed to run in bipolar, 20V span analog output mode as shown in Table I.
Data Input
I AnalogOutput
1111 0000 0001
AnalogOutput Vollage
1111 1100 1000
1111 0000 0000 0000
I + I,(VREFIN) { 2048 2O47}
I I
+ I,(VREFIN)
+9.995IV
+ Full Scale-ILSB + 1/2Scale +ILSB
{ 2048 1O24}
{28}
I .+5.000V
I +4.88mV
I +o.ooov
OBS
+I,(VREFIN)
1000
0000 llli
1 +I,(VREFIN
Zero -ILSB
DA1;A AND CONTROL SIGNAL FORMAT The double buffered registers of the AD392 are addressed by the CS, Al and AO lines. Each rank of registers is 12 bits wide and is presented in a straight offset binary notation. The first rank of registers are loaded sequentially, with valid CS, AI, AO on the trailing rising edge of WR. The second rank of registers, on the other hand, are loaded simultaneously with the data which is in their corresponding first rank registers, with a valid CS and positive pulse of the 2ND UP command. (Note: All second rank registers can be made transparent by tieing the 2ND UP line to a Logic "1".) The data loaded into the second rank registers represents the actual digital code which is on the input of the individual DACs. This data can be read back through the data port, with valid CS, Al and AO, by taking the RD line to a Logic "0". The AD392 also features an asyncronous reset to zero volts for all four DACs by applying a negative pulse to the RESET line. Executing a reset replaces the contents of both ranks of registers with the bipolar zero code (MSB equals Logic "1", all other bits equal Logic "0".)
CS I X 0 0 0 Al X X AO X X WR X X RD X X RESET I 0 I I 2ND Up X X I 0 Output Chip ReadlWrite Disable MSBs Go to I,All OthersGotoO All 2ND Rank Latches Transparent All 2ND Rank Latches Latched ReadBackDACI 2ND Rank
CD
0 ... I en I (') (') 0 !!!1
u
){28}
0111
1111
2048 I -I'(VREFIN) {-L}
I -4.88mV
0100
0000
0000
I
-I'(VREFIN)
{ 2048 1O24}
I
- 5.000V
- 1/2Scale
0000
0000
-I'(VREFIN) g}
I -IO.OOOV
- Full cale S
Table I. AD392 Bipolar Code Table.
The digital portion of the AD392 includes the readback function, control logic and registers all integrated on a custom IC. Data can be latched into anyone of the first rank registers by selecting the correct combination of address lines (AOand AI) and CS. The second rank registers are controlled by the 2ND UP control line. Use of the 2ND UP line enables the DACs to be updated simultaneously. The digital word can be readback from the second rank registers by asserting the correct address lines, 2ND UP and RD command. The RD and WR commands control the bidirectional I/O port. The AD392 features a RESET command for simultaneous update of all DACs to 0 volts out. This is useful for easy system calibration.
OLE
X X 0 X X 0 X X I X X 0 I I 0 0 0 I
U
I
I
0
0
0 I 0 I
I
0 0 0 0
0 I I I
I 0 0 I
U
I
I I I
TE
X X Write to 1ST Rank DACI Read Back DAC2 2ND Rank X X Write to 1ST Rank DAC2 X X ReadBackDAC3 2ND Rank Write to 1ST Rank DAC3
I
0'
I
I
I
X
X
ReadBackDAC4 2ND Rank
Write to 1ST Rank DAC4
0
I
I
ru-
AD392
Symbols: X = Don'tCare I = Logic High 0 = Logic Low
U
= Positive Trailing
Edge Triggered
Table II. AD392 Truth Table
WR AD 2NDUP
+5V
DGND
Figure 1. AD392Block Diagram
-4--
,~() )
OBS
esj
TIMING The timing diagrams (Figures 2 and 3) illustrate the precise relationship between control signals, address signals and the data. The address lines (CS, AI, AO)as well as the data (DO-Dll) must be valid a minimum of l5ns before a WR is executed, and the data must remain valid a minimum of l5ns after the WR has been executed. Minimum pulse width for the WR, 2ND UP and RESET commands is l5ns, Similarly, the address lines (CS, AI, AO)must be valid a minimum of 15ns before a RD is executed. Data will be valid a maximum of 40ns after RD goes low, (Note: This is a MAXIMUM and, therefore, data should be off the bus just before RD goes low to avoid bus contention problems, i.e., damage to the device, data bus oscillations which may result in latching erroneous data in the registers.) Data will be off the bus a maximum of 30ns after RD goes high. (Note: This is a MAXIMUM and, therefore, the data read should be completed just before RD goes high to avoid reading erroneous data.) DAC settling time is measured from the trailing rising edge of the WR signal.
Symbol IDS tw tsu tHD IRS tVR tDDS tBAOn tBAOff t2L! t21.2 t2TR tnn tR"tp
Parameter Device Select Write!UpdatelResetPulse Width Data SetUp Time Data Hold Time Reset Valid for Read Read Valid After Write Device De-Select (from Read Data to Tristate Bus Access On Time Bus Access Off Time Minimum Latch Delay after Write/ Minimum Latch Delay after Next Write! 2ND Rank Transparent for Valid Read 2ND Rank Transparent to DAC Port Outputs Data Rise, Fall Times
Min IS IS IS IS
Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
35 30 40 40 30 10 5 25 0 40 5
NOTES
Timing between pulses measured at 50"A,points. Bus access on rime measured from 50% point of read going low to active high (2.4) or active low (0.4) (see Figures 4 and 5). Bus access off time measured from 50% point of read going high to point at which voltage rrails away from active high or low under standard tristate load conditions (see Figure 6).
Table 11/. ACCharactertics: Voo = 5.0V::!::10%; 05TA5+70C; v,N= VooorDGND
A-i
AI
I
-1 tV"
ViR
2ND UP
DATA IN
TRISTATE
DATA OUT
OLE
--I tm
4
iID
l
'"
~
0 >
3
r
TRISTATE
10
RESET 'DATA IS IN BOTH 1" AND 2NO RANKS uDATA B IS IN 2NORANK. DATA C IS IN 1" RANK
20 ns
30
Figure 4. Typical Bus Access Off Time (tSA Off)
DATA OUT
TE
DATA OUT
40 50
Figure 2. AD392Write/Read Cycle Timing Diagram
mJ
RD
:~ I
TRISTATE
f
I
ITRISTATE
'"
~
0 >
I
I
1--'00'--1 X
TRISTATE
DATA OUT IVO BUSI
\VA--.:::r::.ON
--J
TRISTATE
'"
ON
I)(
RESET CODE
DATA IN (lID BUS)
TRISTATE
RD
10 20 ns 30 40 50
RESET
Figure
3,
r-t,,-J
Figure 5. Typical Bus Access On Time (tSA On)
+5V
IHP6216A VOLTAGE SUPPLY I
AD392 Read Cycle Timing Diagram
TRISTATE OUTPUT
TO SCOPE INPUT TEKTRONIX 7A26 PLUG.IN
RI
RI R2 CI R2
-
= 1.25kH ""%, 1/4W = 100pF, FOR tBA ON
=
15pF, FOR tBA OFF
=
1.35kH
""%,1/4W
P6106A PROBES 7704A MAINFRAME 7B92 TIME BASE OR EQUIVALENT
ALL DIODES IN916 OR EQUIVALENT
DIGITAL GROUND
Figure 6. Standard Tristate Load Circuit
-5-
SETTLING TIME The output amplifiers used in the AD392 are capable of supplying a :t 10 volt swing into a resistive load of 2kD or greater. The settling characteristics of the output amplifier is shown in Figure 7. The test setup used to determine settling time is shown in Figure 8. POWER SUPPLY DECOUPLING The power supplies used with the AD392 should be well filtered and regulated. Internally the + Vcc and - VEEsupplies are independently decoupled about each DAC with O.O39/LFchip capacitors to their corresponding AGND. Therefore, if the grounding scheme of Figure 9 is used, it should be sufficient to place a 4.7/LF tantalum electrolytic capacitor across the + Vcc and - VEE supplies. Decoupling the + VDD supply to DGND should be done in the same manner, however, using a parallel combination ofO.O47/LFceramic and a 4.7/LF tantalum electrolytic capacitor.
the DAC bit input currents are sourced from the + VDDsupply and should return by the shortest possible path and not down the analog return (see Figure 9 for details.).
ADDRESS 8US
RESET
CD
!1:1 0
~
I 0> I M M 0
15V +15V
U
OBS
Figure 7.
AGNO
RETURN
+5V (DIGITAL)
OLE
RETURN
OGNO
2ND UP
RO
WR
Figure
9.AD392Recommended
Circuit Schematic
AD392V0 Settling 20V Step
HP80128 PULSE GEN.
ADDRESS
HPB0128 PULSE DECODE GEN.
3
+5V
AD392 2", UP
-V'>IT""' IHP6216A VOLTAGE SUPPLVI m TEKTRONIX "'>PLUG.IN P6106A PROBE 77OA MAINFRAME 7892 TIME BASE
A' WR
AGND
CIRCUIT DETAILS The following two suggestions are intended to aid the user in the normal operation of the AD392: 1. Bus Termination: The bidirectional tristateable port of the AD392 (as well as the digital inputs) should not be allowed to "float". These functions are provided by a custom CMOS integrated circuit having an input control circuit which is essentially the common gate contact of a pair of P and N channel MOS devices connected in series between the + VDD and DGND supply lines. An unterminated bus allows the gate potential to float to a point where both channels are partially "on" creating an ohmic path across the supply. Therefore, to avoid excessive supply current drain and possible reflections of the digital signal the bus should be terminated in its characteristic impedance to DGND. 2. Digital Signal Integrity and the RESET line: The AD392 has been designed to respond to extremely fast data rates and as a result must operate with a "clean" bus to ensure that valid data is being transmitted (i.e., transients on the bus that cross thresholds with sufficient duration, Sns-lOns, may cause data to become invalid just before a WR command). If the RESET line is not connected to this "clean" bus (i.e., connected to some sort of power on reset circuitry), then it is recommended that this line be decoupled with a minimum of 1O00pfcapacitor to avoid an unwanted asynchronous zero volt reset on all four DACs. If this signal is not used, it should be tied to + VDD at the package.
TE
en ::i ~ 0 w IZ ii: 0..
0.01% FSR = lmV (" ARTIFICIAL SUMMING
NODE
Figure 8. AD392 V0 Settling Time Circuit GROUNDING RULES The AD392 has been designed with four independent DAC analog grounds and a separate digital ground return pin. The analog ground pins are not only the reference points for the individual voltage outputs, they also serve as the return path for the switched DAC bit input currents. These rapidly switching currents may be as large as several milliamps for each DAC and, therefore, should be returned to a low impedance node to avoid code dependent linearity errors, digital-to-analog feedthrough and crosstalk between DAC outputs. It is recommended that all four DAC analog grounds and the digital ground be tied together at the package for optimal performance. + Vcc and - VEEgrounds can be tied together back at the system supply and brought up to the AD392 together, whereas the + VDD ground is tied to the other grounds at the package and not back at the system supply. This configuration is recommended because
-6-

▲Up To Search▲

Price & Availability of AD392

	To Download AD392 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .